Location: Bangalore, India
Experience: 3–15 Years
Salary Range: ₹15–50 LPA
Work Mode: Work from office(380)
Notice Period: Immediate to 60 Days
Role Overview
We are looking for experienced DFT Engineers at Senior/Manager level to work on semiconductor/SoC design projects. The ideal candidate should have a strong understanding of DFT concepts and hands-on experience in one or more areas including BSCAN, MBIST, Scan, ATPG, DFT insertion, pattern generation, and simulation.
The role involves working closely with DFT, RTL, STA, Physical Design, verification, and customer-facing teams. Strong technical debugging, communication, and team mentoring skills are essential.
Must-Have Skills
- Strong understanding of DFT fundamentals and concepts including:
- Scan
- ATPG
- MBIST
- BSCAN
- DFT simulation
- Hands-on experience in at least one of the following:
- MBIST insertion
- Scan insertion
- ATPG pattern generation
- ATPG pattern simulation
- MBIST/BSCAN simulation
- Experience with industry-standard DFT tools from Cadence, Siemens Tessent, or Synopsys.
- Good understanding of fault models such as:
- Stuck-at
- Transition Delay Fault (TDF)
- IDDQ
- Experience with test coverage analysis and coverage improvement techniques.
- Good debugging skills using GUI-based industry-standard simulators such as VCS, NCSim, or Xcelium.
- Experience working at SoC-level DFT.
- Good understanding/experience of DFT implementation concepts such as:
- OCC / OPCG insertion
- EDT / Compression logic
- Clock handling for scan/test modes
- Ability to debug DFT issues and analyze simulation/pattern failures.
- Experience providing test-mode timing constraints to STA and Physical Design teams.
- Strong communication and collaboration skills for working with cross-functional and customer teams.
Nice-to-Have Skills
- Experience with both Zero-Delay and SDF timing simulations.
- Experience with post-silicon bring-up and/or production activities.
- Exposure to tester debug, including analysis of shmoo plots, graphs, and test data.
- Experience in scan test coverage improvement and optimization.
- Broader exposure to multiple DFT domains such as MBIST, BSCAN, Scan, ATPG, and compression.
- Experience leading or mentoring junior/mid-level DFT engineers.
- Experience working directly with customer teams or cross-functional semiconductor teams.
- Understanding of DFT requirements and constraints across RTL, STA, Physical Design, verification, and silicon bring-up stages.
Key Responsibilities
- Develop, implement, and debug DFT solutions for SoC/chip designs.
- Work on Scan, ATPG, MBIST, BSCAN, compression, and related DFT activities based on project requirements.
- Perform ATPG pattern generation, simulation, debugging, and coverage analysis.
- Support DFT insertion and verification using industry-standard tools.
- Analyze and resolve DFT simulation and pattern failures.
- Improve test coverage and identify opportunities for DFT optimization.
- Support OCC/OPCG, EDT/compression, and scan clock-related implementation activities.
- Perform and debug Zero-Delay and SDF simulations where required.
- Coordinate with STA and Physical Design teams to define and implement test-mode timing constraints.
- Support post-silicon bring-up and production/test debug activities where applicable.
- Collaborate with RTL, verification, STA, Physical Design, and other cross-functional teams.
- Communicate technical issues, debug findings, and project status effectively.
- For senior/manager-level candidates, provide technical guidance, mentoring, and support to DFT engineers.
Candidate Profile
The Ideal Candidate Will Have
- 3–15 years of relevant DFT/VLSI experience.
- Strong hands-on DFT knowledge with experience in at least one major DFT domain.
- Strong analytical and debugging capabilities.
- Ability to work independently as well as within cross-functional teams.
- Good verbal and written communication skills.
- Willingness to work from office, hybrid, or remote depending on project requirements.
- Preferably, a stable career history with at least 2 years in previous/current organizations.
Interview Process
- 2–3 rounds of virtual technical interviews
- HR discussion
Working Hours: Regular working hours
Skills: fault models,dft fundamentals,dft tools,scan insertion,xcelium,ncsim,iddq,bscan,atpg pattern generation,transition delay fault,atpg,vcs,mbist insertion,soc-level dft,scan,dft implementation,stuck-at,concepts,mbist,dft simulation