Company:
Qualcomm Vietnam Company Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
The SoC Design organization is seeking engineers to contribute to the implementation and front-end readiness of complex SoC, subsystem, and IP designs. This role focuses on design constraints, synthesis, timing analysis, power-intent implementation, and implementation collateral required to deliver high-quality netlists to downstream Physical Design, Design Verification, DFT, emulation, and signoff teams.
The successful candidate will work closely with RTL Design, SoC Architecture, Design Verification, Physical Design, DFT, CAD/methodology, power-management, and program teams across the global engineering organization.
The role requires a strong understanding of the transformation from RTL to synthesized netlist, including constraint development, synthesis optimization, timing and QoR analysis, low-power implementation using UPF, and resolution of design issues across RTL, constraints, libraries, tools, and flow configuration.
I. Responsibilities
Design Implementation and Front-End Readiness
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Support implementation of complex SoC, subsystem, and IP designs from RTL through synthesis and handoff to downstream implementation teams.
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Review RTL hierarchy, design partitioning, clock and reset architecture, interface definitions, and implementation requirements.
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Prepare and maintain synthesis scripts, design configuration, file lists, libraries, operating conditions, scenarios, and implementation collateral.
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Coordinate design releases, dependencies, configuration updates, and implementation readiness across RTL, DV, DFT, PD, CAD, and architecture teams.
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Analyze design quality and identify RTL, constraint, library, or flow issues affecting timing, power, area, reliability, or implementation convergence.
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Support design reviews, implementation reviews, signoff reviews, and technical documentation activities.
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Investigate failures across RTL, synthesis, constraints, UPF, libraries, tool setup, and build environments; identify root cause and drive corrective action.
Constraint Development and Timing Readiness
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Develop, review, and maintain timing constraints for block, subsystem, and SoC-level designs.
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Create and validate clocks, generated clocks, clock relationships, clock uncertainty, input/output delays, loads, drive models, and operating scenarios.
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Define and review timing exceptions, including false paths, multicycle paths, asynchronous paths, clock groups, and case analysis.
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Support multi-mode, multi-corner timing analysis and ensure constraints are complete, consistent, and aligned with design intent.
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Analyze timing reports, path groups, startpoints, endpoints, slack, path exceptions, clock latency, skew, and constraint coverage.
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Debug unconstrained paths, invalid constraints, conflicting exceptions, missing clocks, generated-clock issues, and constraint-propagation problems.
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Collaborate with RTL and Physical Design teams to resolve critical paths, high-fanout issues, excessive buffering, logic depth, congestion risks, and timing-convergence challenges.
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Review constraints for synthesis, formal equivalence, DFT, static timing analysis, and physical implementation consistency.
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Develop constraint-quality checks and automation to improve constraint completeness, consistency, and reuse across projects.
Synthesis and Netlist Generation
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Run and debug RTL synthesis for blocks, subsystems, and SoC-level designs using industry-standard synthesis flows.
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Generate and review synthesis netlists, reports, databases, timing views, and implementation handoff collateral.
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Analyze synthesis results for timing, area, power, high-fanout nets, unmapped logic, inferred structures, unconnected signals, and optimization quality.
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Tune synthesis options, compile strategies, effort levels, retiming or optimization settings, and flow configuration to improve QoR while preserving design intent.
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Identify and resolve issues involving black boxes, missing or mismatched libraries, unresolved references, unintended latches, X-propagation, multiple drivers, and synthesis warnings.
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Support synthesis quality-of-results tracking and compare changes across RTL, constraints, libraries, tool versions, and implementation configurations.
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Deliver clean, traceable, and reproducible netlists for Physical Design, DFT, formal equivalence, emulation, gate-level simulation, and signoff activities.
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Partner with RTL designers to recommend RTL changes that improve timing, area, power, synthesis quality, and downstream implementation convergence.
Experience with UPF and low-power implementation is a plus
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Develop, integrate, review, and maintain UPF-based power intent for blocks, subsystems, and SoC designs.
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Define and validate power domains, supply networks, supply sets, power states, isolation strategies, level-shifter strategies, retention requirements, and related low-power structures.
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Ensure UPF intent is consistent with RTL hierarchy, power architecture, voltage domains, clock/reset behavior, and implementation requirements.
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Run and debug power-intent checks, including missing or conflicting supplies, invalid domain crossings, incorrect isolation placement, level-shifter issues, retention mismatches, and incomplete power-state definitions.
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Analyze synthesis results involving isolation cells, level shifters, retention cells, always-on logic, power switches, and other low-power implementation elements.
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Collaborate with architecture, RTL, PD, DFT, verification, and power-management teams to resolve power-intent interpretation and implementation issues.
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Support low-power equivalence, power-aware simulation, implementation handoff, and signoff readiness.
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Improve UPF methodology, reusable templates, validation checks, and automation across projects.
Quality, Debug, and Cross-Functional Collaboration
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Drive implementation quality closure across lint, CDC/RDC, connectivity, synthesis, constraints, UPF, formal, and release-readiness checks.
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Debug tool failures and design-quality issues using logs, reports, databases, waveforms, and automated analysis.
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Work with CAD and methodology teams to improve flow robustness, runtime, capacity, repeatability, and ease of adoption.
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Document implementation assumptions, constraints, exceptions, known issues, methodology decisions, and handoff requirements.
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Mentor engineers and share best practices in synthesis, timing constraints, UPF, debug, automation, and implementation methodology.
II. Level Expectations
Engineer
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Execute assigned implementation, constraint, synthesis, and UPF tasks with guidance from senior engineers.
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Analyze basic timing, synthesis, and power-intent reports and assist with issue triage and closure.
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Maintain scripts, configuration, reports, and implementation collateral according to established methodology.
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Collaborate effectively with partner teams and escalate issues with clear technical information.
Senior Engineer
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Independently own implementation activities for blocks or subsystems from setup through synthesis and handoff.
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Develop and validate timing constraints, synthesis flows, and UPF implementation for assigned design areas.
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Drive root-cause analysis and closure of timing, QoR, power-intent, and flow issues across multiple teams.
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Contribute to methodology improvements, automation, technical reviews, and mentoring.
Staff /Senior Staff Engineer
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Lead implementation of major subsystems or complex SoC design areas, including constraints, synthesis, and low-power intent.
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Define technical plans, implementation strategy, quality criteria, and handoff requirements.
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Resolve complex cross-functional issues involving RTL, architecture, tools, libraries, timing, power, and physical implementation.
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Drive reusable methodology, automation, QoR improvement, and technical alignment across projects.
Principal Engineer
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Establish technical direction for SoC design implementation, synthesis, constraints, and UPF methodology across programs.
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Lead architecture-level decisions that affect timing closure, power intent, implementation convergence, and design quality.
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Influence cross-functional organizations and resolve the most complex technical risks and escalations.
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Define scalable flows, standards, automation, and best practices for future SoC programs and mentor senior technical leaders.
III. Minimum Qualifications
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Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a Master’s degree is preferred.
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3+ years of relevant experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or front-end implementation.
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Experience with at least one RTL development or front-end implementation flow from design through synthesis or implementation handoff.
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Knowledge of Verilog or SystemVerilog and familiarity with RTL design and SoC integration concepts.
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Experience developing or reviewing timing constraints and analyzing synthesis or static timing reports.
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Understanding of clocks, resets, interfaces, timing exceptions, design hierarchy, and implementation tradeoffs.
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Good communication, problem-solving, ownership, and cross-functional collaboration skills.
Preferred Qualifications
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Experience with synthesis tools, static timing analysis tools, equivalence checking, lint, CDC/RDC, or related front-end quality tools.
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Practical experience with UPF, power domains, isolation, level shifters, retention, power states, or power-aware verification.
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Experience with multi-mode, multi-corner constraints and timing closure across block, subsystem, or SoC designs.
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Knowledge of ASIC implementation flows, DFT, physical design handoff, emulation, FPGA prototyping, or gate-level simulation.
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Proficiency in Tcl, Python, Perl, Shell, or similar scripting languages for flow automation and report analysis.
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Experience with AXI, AHB, APB, or other standard on-chip interfaces.
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Experience working in a large, globally distributed semiconductor engineering organization.
IV. Technical Skills
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RTL: Verilog, SystemVerilog, RTL hierarchy, clock/reset structures, interface integration, and synthesis coding practices.
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Constraints: clocks, generated clocks, I/O delays, exceptions, clock groups, uncertainty, scenarios, and constraint validation.
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Synthesis: RTL-to-gate compilation, QoR analysis, timing/area/power optimization, netlist generation, and synthesis debug.
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Low Power: UPF, power domains, supply sets, isolation, level shifters, retention, power states, and power-aware implementation.
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Quality and Signoff: lint, CDC/RDC, formal connectivity, equivalence, timing analysis, gate-level simulation, and implementation handoff.
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Automation: Tcl, Python, Perl, Shell, report parsing, flow integration, regression infrastructure, and methodology development.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
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