ID: DFT-3
Description
As a DFT Engineer, you will collaborate in the DFT implementation process, ensuring seamless integration with test validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production.
Key Responsibilities
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Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability.
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Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces.
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Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.
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Test Development & Implementation
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Develop and implement test plans and test strategies at silicon, package, and system levels.
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Define and develop automated test solutions for production and characterization.
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Ensure test coverage for all product development stages, from pre-silicon to mass production.
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Guarantee high yield on the final solution while considering chiplet complexities.
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Cross-Functional Collaboration
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Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.
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Collaborate with product management to ensure alignment with customer requirements and timelines.
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Process Improvement & Innovation
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Continuously explore and implement new DFT methodologies and manufacturing processes.
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Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.
Why Seynamics?
Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Se
- ynamics.
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Accelerated development path.
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4 days per week in the Barcelona office (city center), 1 day WFH.
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1 week of work from everywhere in the world.
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Competitive package.
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A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.
Requirements
- Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field.
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4+ years of related experience
Must have - experience with Tessent and SSN methods integrated with
- ing EDA design flows for advanced technology nodes is a plus.
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Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production.
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Strong background in post-silicon test optimization and yield analysis.
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Experience in defining and implementing test strategies for high-volume production.
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Proficiency in RTL and testbench development using SystemVerilog and Verilog.
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Strong scripting skills (Shell, Tcl, Python3).
MID