A high-growth global Deep-Tech innovator developing next-generation compute architectures for High-Performance Computing (HPC) and supercomputing applications.
The company engineers advanced, adaptive-algorithm compute solutions engineered to dramatically accelerate complex computational workloads across artificial intelligence, aerospace, medicine, energy, and defense.
Backed by substantial funding totaling hundreds of millions of dollars from premier global investors, the organization operates with a global workforce of hundreds of professionals, pairing deep scientific research with large-scale silicon engineering.
The company is located in Tel Aviv and operates on a flexible hybrid work model with two days working from home.
Role Description-
- Serving as a Digital / RTL Design Team Lead, leading a focused engineering team of 3–5 designers while remaining heavily Hands-on in end-to-end chip design.
- Driving the full design lifecycle from interpreting high-level architectural requirements to defining Micro-Architecture and Technical Specifications, through to critical block implementation in RTL and post-silicon validation support.
- Designing high-throughput, mission-critical silicon subsystems with a strong emphasis on High-Speed and Low-Power optimization.
- Conducting hands-on implementation and front-end design quality checks, including RTL coding, CDC (Clock Domain Crossing), Lint, Simulation, and Power Analysis.
- Collaborating cross-functionally with Architecture, Verification, Physical Design (Backend), and Software engineering groups to ensure seamless silicon tape-out and execution.
- Providing direct mentorship, project management, design reviews, and technical leadership to team members.
Requirements-
- 2 years of experience in team management / engineering leadership – Mandatory
- 7 years of hands-on experience as a Digital Design / Logic Design / RTL / ASIC / VLSI Design Engineer – Mandatory
- Deep, practical track record in micro-architecture specification and RTL design for complex digital blocks – Mandatory
- Hands-on proficiency with digital design front-end flows: Lint, CDC, Simulation, and Power Analysis – Mandatory
- Proven experience designing for High-Speed and Low-Power constraints – Mandatory
- Academic Degree (B.Sc.) in Electrical Engineering, Computer Engineering, or equivalent technical discipline – Mandatory