Job Title: Senior Emulation Engineer
Exp: 10+ years
Location: San Jose, CA
Duration: Fulltime & Contract
Key Skills:
- Key Skills: Siemens Veloce (Strato / Primo / VirtuaLAB) — Mandatory. Hands-on experience with PCIe, UCIe, LPDDR, and HBM protocols.
- Platform Requirement: 7+ years of SoC design experience with a strict focus on Siemens Veloce emulation setups and environment bring-up. (Familiarity with Palladium/ZeBu or HAPS/Protium is a plus, but Veloce mastery is required).
Set up and maintain Siemens Veloce emulation and prototyping platforms
Adapt SoC designs for Emulation and Prototyping
Develop and debug emulation testbenches and system-level environments
Support pre-silicon validation, power/performance analysis, and early software
bring-up. Participate in silicon bring-up and validation.
Collaborate with design and verification teams to isolate design issues and accelerate debug.
Optimize performance of the emulation workloads and reduce turnaround time.
Work with firmware/software teams to enable use of emulators for OS and driver testing.
5 to 10 years of experience
- BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.
- Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based
- prototyping systems (proFPGA, HAPS, or Protium)
- Experience with emulating high speed I/O interfaces such as PCIe and UCIe and
- memory technologies such as LPDDR and HBM
- Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.
- Proficiency in hardware debug tools, waveform viewers, and logic analyzers
- Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development.
- Familiarity with UVM, simulation, and testbench environments. SystemVerilog and
- UVM-based verification experience a plus
- Hands-on software development experience with C/C++ is a plus
Regards
Rohit
737 304 7465